SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register allows controlling various parameters of the OCP interface.
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| Instance Name | Physical Address |
|---|---|
| MCSPI0 | 2010 0110h |
| MCSPI1 | 2011 0110h |
| MCSPI2 | 2012 0110h |
| MCSPI3 | 2013 0110h |
| MCSPI4 | 2014 0110h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_14 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_14 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_14 | CLOCKACTIVITY | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_15 | SIDLEMODE | ENAWAKEUP | SOFTRESET | AUTOIDLE | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 2h | 1h | 0h | 1h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:10 | RESERVED_14 | R | 0h | Reads returns 0 |
| 9:8 | CLOCKACTIVITY | R/W | 0h | Clocks activity during wake up mode period 0 Interface and functional clocks may be
switched off.
1 Interface clock is maintained. Functional
clock may be switched off.
2 Functional clock is maintained. Interface
clock may be switched off.
3 Interface and functional clocks are
maintained. |
| 7:5 | RESERVED_15 | R | 0h | Reads returns 0 |
| 4:3 | SIDLEMODE | R/W | 2h | Power management 0 If an IDLE request is detected, the MCSPI
acknowledges it unconditionally and goes in
inactive mode. Interrupt, DMA requests and
wake-up lines are unconditionally
deasserted and the module wake-up
capability is deactivated even if the
MCSPI_SYSCONFIG[2] ENAWAKEUP bit is set.
1 If an IDLE request is detected, the request
is ignored and the module does not switch
to wake-up mode, and keeps on behaving
normally.
2 If an IDLE request is detected, the module
will switch to wake-up mode based on its
internal activity, and the wake-up
capability can be used if the bit
MCSPI_SYSCONFIG[2] ENAWAKEUP is set.
3 Reserved - do not use. |
| 2 | ENAWAKEUP | R/W | 1h | WakeUp feature control 0 Wake-up capability is disabled. 1 Wake-up capability is enabled. |
| 1 | SOFTRESET | R/W | 0h | Software reset During reads it always returns 0 0 (write) Normal mode
1 (write) Set this bit to 1 to trigger a
module reset. The bit is automatically
reset by the hardware. |
| 0 | AUTOIDLE | R/W | 1h | Internal OCP Clock gating strategy 0 Interface clock is free-running.
1 Automatic interface clock gating strategy
is applied, based on the configuration
interface activity. |