SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Digital Watchdog Preload Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5094h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DWDPRLD | ||||||
| NONE | R/W | ||||||
| 0h | FFFh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DWDPRLD | |||||||
| R/W | |||||||
| FFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | RESERVED | NONE | 0h | Reserved |
| 11:0 | DWDPRLD | R/W | FFFh | User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left- justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 213 / RTICLK1 where: RTIDWDPRLD = 0...4095 Reset Source: sms_custom_rst_mod_g_rst_n |