SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RTI Clear/Status Interrupt Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5084h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CLEAROVL1INT | CLEAROVL0INT | CLEARTBINT | ||||
| NONE | R/W1TC | R/W1TC | R/W1TC | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CLEARDMA3 | CLEARDMA2 | CLEARDMA1 | CLEARDMA0 | |||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLEARINT3 | CLEARINT2 | CLEARINT1 | CLEARINT0 | |||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18 | CLEAROVL1INT | R/W1TC | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 17 | CLEAROVL0INT | R/W1TC | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 16 | CLEARTBINT | R/W1TC | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11 | CLEARDMA3 | R/W1TC | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 10 | CLEARDMA2 | R/W1TC | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 9 | CLEARDMA1 | R/W1TC | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 8 | CLEARDMA0 | R/W1TC | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3 | CLEARINT3 | R/W1TC | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 2 | CLEARINT2 | R/W1TC | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 1 | CLEARINT1 | R/W1TC | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 0 | CLEARINT0 | R/W1TC | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |