SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RTI Update Compare 0 Register
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5054h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| UDCP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| UDCP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| UDCP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| UDCP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | UDCP0 | R/W | 0h | This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value Reset Source: sms_custom_rst_mod_g_rst_n |