SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RTI Compare 0 Register
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5050h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| COMP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| COMP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| COMP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | COMP0 | R/W | 0h | This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. Reset Source: sms_custom_rst_mod_g_rst_n |