SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RTI Compare Up Counter 0 Register
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CPUC0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CPUC0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CPUC0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CPUC0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CPUC0 | R/W | 0h | This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: fFRC0 = R-----T---I---C----L----K-- 232 If CPUC0 0: fFRC0 = ----R----T----I--C-----L---K------- CPUC0 + 1 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Reset Source: sms_custom_rst_mod_g_rst_n |