SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register provides specific control for the individual module. One register per module on the device.
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| Instance Name | Physical Address |
|---|---|
| WKUP_PSC0 | 0400 0A00h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| FORCE | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESETISO | BLKCHIP1RST | EMUIHBIE | EMURSTIE | LRSTZ | ||
| NONE | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | NEXT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | FORCE | R/W | 0h | Force Bit 0 No force 1 Force |
| 30:13 | RESERVED | NONE | 0h | Reserved |
| 12 | RESETISO | R/W | 0h | Reset Isolation 0 No reset isolation 1 Enable reset isolation |
| 11 | BLKCHIP1RST | R/W | 0h | Block Chip_1_Reset Reset Source: chip_rst.chip_1_rst_n |
| 10 | EMUIHBIE | R/W | 0h | Emulation Alters Module State. Inhibits Module Inactive or Force Module Active. 0 Not enabled 1 Interrupt enabled |
| 9 | EMURSTIE | R/W | 0h | Emulation Alter Reset Interrupt Enable 0 Not enabled 1 Interrupt enabled |
| 8 | LRSTZ | R/W | 0h | Module local reset control 0 assert local reset 1 de-assert local reset |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | NEXT | R/W | 0h | Module Next State
Only key states can be selected in this field.
If a Reserved value is programmed into MDCTL.NEXT, hardware will internally force the state to SwRstDisable.
If MDCFG.PERMDIS = 1, the module must remain in SwRstDisable after hardware places it in SwRstDisable state. The user is allowed to write this field but hardware ignores this field and always passes along MDCTL.NEXT = SwRstDisable. 4 AutoSleep 5 AutoWake 2 Disable 3 Enable 0 SwRstDisable 1 SyncRst Other Reserved s |