SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is user programmable. It holds the counter values for rail counter. User can select one of the two counter values to be used for each power domain (see RAILSEL register).
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| Instance Name | Physical Address |
|---|---|
| WKUP_PSC0 | 0400 0104h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RAILCTR1 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAILCTR0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:8 | RAILCTR1 | R/W | 0h | Rail Counter Value 1 Reset Source: chip_rst.chip_1_rst_n |
| 7:0 | RAILCTR0 | R/W | 0h | Rail Counter Value 0 Reset Source: chip_rst.chip_1_rst_n |