SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register has no storage. Read from this register returns 0. Each bit represents one module (index 0 for modules 0-31, index 1 for modules 32-63, etc.).
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| Instance Name | Physical Address |
|---|---|
| WKUP_PSC0 | 0400 0050h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| M | |||||||
| W1TC | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| M | |||||||
| W1TC | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| M | |||||||
| W1TC | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| M | |||||||
| W1TC | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | M | W1TC | 0h | Write of 1 clears the corresponding MERRPR bit. Reset Source: chip_rst.chip_1_rst_n |