SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RESET the PULSAR EVNT BUS ESM events
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| Instance Name | Physical Address |
|---|---|
| R5FSS0_COMMON0 | 05B0 101Ch |
| R5FSS1_COMMON0 | 05B2 101Ch |
| WKUP_R5FSS0_COMMON0 | 3C01 801Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CPU1_EB6_MULTIPLE_BIT_ERROR | CPU1_EB5_MULTIPLE_BIT_ERROR | CPU1_EB4_MULTIPLE_BIT_ERROR | CPU1_EB3_MULTIPLE_BIT_ERROR | CPU1_EB2_MULTIPLE_BIT_ERROR | CPU1_EB1_MULTIPLE_BIT_ERROR | CPU1_EB0_MULTIPLE_BIT_ERROR | CPU1_EB8_SINGLE_BIT_ERROR |
| R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CPU1_EB7_SINGLE_BIT_ERROR | CPU1_EB6_SINGLE_BIT_ERROR | CPU1_EB5_SINGLE_BIT_ERROR | CPU1_EB4_SINGLE_BIT_ERROR | CPU1_EB3_SINGLE_BIT_ERROR | CPU1_EB2_SINGLE_BIT_ERROR | CPU1_EB1_SINGLE_BIT_ERROR | CPU1_EB0_SINGLE_BIT_ERROR |
| R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CPU0_EB6_MULTIPLE_BIT_ERROR | CPU0_EB5_MULTIPLE_BIT_ERROR | CPU0_EB4_MULTIPLE_BIT_ERROR | CPU0_EB3_MULTIPLE_BIT_ERROR | CPU0_EB2_MULTIPLE_BIT_ERROR | CPU0_EB1_MULTIPLE_BIT_ERROR | CPU0_EB0_MULTIPLE_BIT_ERROR | CPU0_EB8_SINGLE_BIT_ERROR |
| R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CPU0_EB7_SINGLE_BIT_ERROR | CPU0_EB6_SINGLE_BIT_ERROR | CPU0_EB5_SINGLE_BIT_ERROR | CPU0_EB4_SINGLE_BIT_ERROR | CPU0_EB3_SINGLE_BIT_ERROR | CPU0_EB2_SINGLE_BIT_ERROR | CPU0_EB1_SINGLE_BIT_ERROR | CPU0_EB0_SINGLE_BIT_ERROR |
| R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD | R/W1TD |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CPU1_EB6_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 31 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 30 | CPU1_EB5_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 30 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 29 | CPU1_EB4_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 29 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 28 | CPU1_EB3_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 28 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 27 | CPU1_EB2_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 27 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 26 | CPU1_EB1_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 26 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 25 | CPU1_EB0_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 25 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 24 | CPU1_EB8_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 24 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 23 | CPU1_EB7_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 23 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 22 | CPU1_EB6_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 22 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 21 | CPU1_EB5_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 21 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 20 | CPU1_EB4_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 20 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 19 | CPU1_EB3_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 19 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 18 | CPU1_EB2_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 18 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 17 | CPU1_EB1_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 17 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 16 | CPU1_EB0_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU1 Event Bus 16 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 15 | CPU0_EB6_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 15 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 14 | CPU0_EB5_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 14 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 13 | CPU0_EB4_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 13 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 12 | CPU0_EB3_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 12 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 11 | CPU0_EB2_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 11 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 10 | CPU0_EB1_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 10 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 9 | CPU0_EB0_MULTIPLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 9 MULTIPLE BIT Error Counter Reset Source: mod_g_rst_n |
| 8 | CPU0_EB8_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 8 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 7 | CPU0_EB7_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 7 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 6 | CPU0_EB6_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 6 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 5 | CPU0_EB5_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 5 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 4 | CPU0_EB4_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 4 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 3 | CPU0_EB3_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 3 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 2 | CPU0_EB2_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 2 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 1 | CPU0_EB1_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 1 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |
| 0 | CPU0_EB0_SINGLE_BIT_ERROR | R/W1TD | 0h | Decrement CPU0 Event Bus 0 SINGLE BIT Error Counter Reset Source: mod_g_rst_n |