SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
SET the PULSAR EVNT BUS ESM events
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| Instance Name | Physical Address |
|---|---|
| R5FSS0_COMMON0 | 05B0 1018h |
| R5FSS1_COMMON0 | 05B2 1018h |
| WKUP_R5FSS0_COMMON0 | 3C01 8018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CPU1_MULTIPLE_BIT_ERROR | CPU1_SINGLE_BIT_ERROR | CPU0_MULTIPLE_BIT_ERROR | CPU0_SINGLE_BIT_ERROR | |||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3 | CPU1_MULTIPLE_BIT_ERROR | R/W1TS | 0h | SET CPU1 multiple bit errors ESM event Reset Source: mod_g_rst_n |
| 2 | CPU1_SINGLE_BIT_ERROR | R/W1TS | 0h | SET CPU1 single bit errors ESM event Reset Source: mod_g_rst_n |
| 1 | CPU0_MULTIPLE_BIT_ERROR | R/W1TS | 0h | SET CPU0 multiple bit error ESM event Reset Source: mod_g_rst_n |
| 0 | CPU0_SINGLE_BIT_ERROR | R/W1TS | 0h | SET CPU0 single bit error ESM event Reset Source: mod_g_rst_n |