SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Buffer Configuration register
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| Instance Name | Physical Address |
|---|---|
| I2C0 | 2000 0094h |
| I2C1 | 2001 0094h |
| I2C2 | 2002 0094h |
| I2C3 | 2003 0094h |
| I2C4 | 2004 0094h |
| I2C5 | 2005 0094h |
| I2C6 | 2006 0094h |
| WKUP_I2C0 | 2B20 0094h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RDMA_EN | RXFIFO_CLR | RXTRSH | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| XDMA_EN | TXFIFO_CLR | TXTRSH | |||||
| R/W | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | RDMA_EN | R/W | 0h | Receive DMA channel enable |
| 14 | RXFIFO_CLR | R/W | 0h | Receive FIFO clear |
| 13:8 | RXTRSH | R/W | 0h | Threshold value for FIFO buffer in RX mode |
| 7 | XDMA_EN | R/W | 0h | Transmit DMA channel enable |
| 6 | TXFIFO_CLR | R/W | 0h | Transmit FIFO clear |
| 5:0 | TXTRSH | R/W | 0h | Threshold value for FIFO buffer in TX mode |