SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Per-event DMA TX wakeup enable.
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| Instance Name | Physical Address |
|---|---|
| I2C0 | 2000 004Ch |
| I2C1 | 2001 004Ch |
| I2C2 | 2002 004Ch |
| I2C3 | 2003 004Ch |
| I2C4 | 2004 004Ch |
| I2C5 | 2005 004Ch |
| I2C6 | 2006 004Ch |
| WKUP_I2C0 | 2B20 004Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | XDR | RDR | RESERVED3 | ROVR | XUDF | AAS | BF |
| R | R/W | R/W | R | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED2 | STC | GC | RESERVED1 | DRDY | ARDY | NACK | AL |
| R | R/W | R/W | R | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | RESERVED | R | 0h | Reserved |
| 14 | XDR | R/W | 0h | Transmit Draining wakeup set |
| 13 | RDR | R/W | 0h | Receive Draining wakeup set |
| 12 | RESERVED3 | R | 0h | Reserved |
| 11 | ROVR | R/W | 0h | Receive overrun wakeup set |
| 10 | XUDF | R/W | 0h | Transmit underflow wakeup set |
| 9 | AAS | R/W | 0h | Address as target IRQ wakeup set |
| 8 | BF | R/W | 0h | Bus Free IRQ wakeup set |
| 7 | RESERVED2 | R | 0h | Reserved |
| 6 | STC | R/W | 0h | Start Condition IRQ wakeup set |
| 5 | GC | R/W | 0h | General call IRQ wakeup set |
| 4 | RESERVED1 | R | 0h | Reserved |
| 3 | DRDY | R/W | 0h | Receive/Transmit data ready IRQ wakeup set |
| 2 | ARDY | R/W | 0h | Register access ready IRQ wakeup set |
| 1 | NACK | R/W | 0h | No acknowledgment IRQ wakeup set |
| 0 | AL | R/W | 0h | Arbitration lost IRQ wakeup set |