SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Per-event interrupt enable bit vector.
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| Instance Name | Physical Address |
|---|---|
| I2C0 | 2000 002Ch |
| I2C1 | 2001 002Ch |
| I2C2 | 2002 002Ch |
| I2C3 | 2003 002Ch |
| I2C4 | 2004 002Ch |
| I2C5 | 2005 002Ch |
| I2C6 | 2006 002Ch |
| WKUP_I2C0 | 2B20 002Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_5 | XDR_IE | RDR_IE | RESERVED1 | ROVR | XUDF | ASS_IE | BF_IE |
| R/W | R/W | R/W | R | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AERR_IE | STC_IE | GC_IE | XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE | AL_IE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | RESERVED_5 | R/W | 0h | Write 0s for future compatibility Read returns 0 |
| 14 | XDR_IE | R/W | 0h | Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR] |
| 13 | RDR_IE | R/W | 0h | Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR] |
| 12 | RESERVED1 | R | 0h | reserved |
| 11 | ROVR | R/W | 0h | Receive overrun enable set |
| 10 | XUDF | R/W | 0h | Transmit underflow enable set |
| 9 | ASS_IE | R/W | 0h | Addressed as Target interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS] |
| 8 | BF_IE | R/W | 0h | Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF] |
| 7 | AERR_IE | R/W | 0h | Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR] |
| 6 | STC_IE | R/W | 0h | Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC] |
| 5 | GC_IE | R/W | 0h | General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC] |
| 4 | XRDY_IE | R/W | 0h | Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY] |
| 3 | RRDY_IE | R/W | 0h | Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY] |
| 2 | ARDY_IE | R/W | 0h | Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY] |
| 1 | NACK_IE | R/W | 0h | No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK] |
| 0 | AL_IE | R/W | 0h | Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL] |