SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Per-event raw interrupt status vector
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| Instance Name | Physical Address |
|---|---|
| I2C0 | 2000 0024h |
| I2C1 | 2001 0024h |
| I2C2 | 2002 0024h |
| I2C3 | 2003 0024h |
| I2C4 | 2004 0024h |
| I2C5 | 2005 0024h |
| I2C6 | 2006 0024h |
| WKUP_I2C0 | 2B20 0024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_11 | XDR | RDR | BB | ROVR | XUDF | AAS | BF |
| R/W | R/W | R/W | R | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AERR | STC | GC | XRDY | RRDY | ARDY | NACK | AL |
| R/W | R/W | R/W1C | R/W1C | R/W1C | R/W1C | R/W1C | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | RESERVED_11 | R/W | 0h | Write 0s for future compatibility Read returns 0 |
| 14 | XDR | R/W | 0h | Transmit draining IRQ status |
| 13 | RDR | R/W | 0h | Receive draining IRQ status |
| 12 | BB | R | 0h | Bus busy statusWriting into this bit has no effect |
| 11 | ROVR | R/W | 0h | Receive overrun statusWriting into this bit has no effect |
| 10 | XUDF | R/W | 0h | Transmit underflow statusWriting into this bit has no effect |
| 9 | AAS | R/W | 0h | Address recognized as target IRQ status |
| 8 | BF | R/W | 0h | Bus Free IRQ status |
| 7 | AERR | R/W | 0h | Access Error IRQ status |
| 6 | STC | R/W | 0h | Start Condition IRQ status |
| 5 | GC | R/W1C | 0h | General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear |
| 4 | XRDY | R/W1C | 0h | Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
| 3 | RRDY | R/W1C | 0h | Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
| 2 | ARDY | R/W1C | 0h | Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear |
| 1 | NACK | R/W1C | 0h | No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit |
| 0 | AL | R/W | 0h | Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in controller transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0 |