SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event. Note for device-specific registers: Accessing XEVTCTL not implemented on a specific device may cause improper device operation.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 00CCh |
| MCASP1 | 02B1 00CCh |
| MCASP2 | 02B2 00CCh |
| MCASP3 | 02B3 00CCh |
| MCASP4 | 02B4 00CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED110 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED110 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED110 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED110 | XDATDMA | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED110 | R | 0h | |
| 0 | XDATDMA | R/W | 0h | Transmit data DMA request enable bit. If Writing to this bit, always write the default value of 0. 0 Transmit data DMA request is enabled. 1 Reserved |