SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 00C8h |
| MCASP1 | 02B1 00C8h |
| MCASP2 | 02B2 00C8h |
| MCASP3 | 02B3 00C8h |
| MCASP4 | 02B4 00C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| XCNT | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| XMAX | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| XMIN | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED109 | XPS | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | XCNT | R | 0h | Transmit clock count value [from previous measurement]. The clock circuit continually counts the number of system clocks for every 32 transmit high-frequency controller clock [AHCLKX] signals, and stores the count in XCNT until the next measurement is taken. |
| 23:16 | XMAX | R/W | 0h | Transmit clock maximum boundary. This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency controller clock [AHCLKX] signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic. |
| 15:8 | XMIN | R/W | 0h | Transmit clock minimum boundary. This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency controller clock [AHCLKX] signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic. |
| 7:4 | RESERVED109 | R | 0h | |
| 3:0 | XPS | R/W | 0h | Transmit clock check prescaler value. Fh = Reserved from 9h to Fh. 0 McASP system clock divided by 1. 1 McASP system clock divided by 2. 2 McASP system clock divided by 4. 3 McASP system clock divided by 8. 4 McASP system clock divided by 16. 5 McASP system clock divided by 32. 6 McASP system clock divided by 64. 7 McASP system clock divided by 128. 8 McASP system clock divided by 256. 9 Reserved from 9h to Fh. |