SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency controller clock (AHCLKX) and the transmit clock generator.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 00B4h |
| MCASP1 | 02B1 00B4h |
| MCASP2 | 02B2 00B4h |
| MCASP3 | 02B3 00B4h |
| MCASP4 | 02B4 00B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED104 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED104 | BUSY | DIVBUSY | ADJBUSY | HCLKXADJ | |||
| R/W | R/W | R/W | R/W | W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HCLKXM | HCLKXP | RESERVED103 | HCLKXDIV | ||||
| R/W | R/W | R | R/W | ||||
| 1h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HCLKXDIV | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:21 | RESERVED104 | R/W | 0h | |
| 20 | BUSY | R/W | 0h | Status: logical OR of DIVBUSY, ADJBUSY |
| 19 | DIVBUSY | R/W | 0h | Status: divide ratio change in progress? |
| 18 | ADJBUSY | R/W | 0h | Status: one-shot adjustment in progress? |
| 17:16 | HCLKXADJ | W | 0h | HCLKXDIV one-shot adjustment |
| 15 | HCLKXM | R/W | 1h | Transmit high-frequency clock source bit. 0 External transmit high-frequency clock
source from AHCLKX pin.
1 Internal transmit high-frequency clock
source from output of programmable high
clock divider. |
| 14 | HCLKXP | R/W | 0h | Transmit bitstream high-frequency clock polarity select bit. 0 AHCLKX is not inverted before programmable
bit clock divider. In the special case
where the transmit bit clock (ACLKX) is
internally generated and the programmable
bit clock divider is set to divide-by-1
(CLKXDIV = 0 in ACLKXCTL), AHCLKX is
directly passed through to the ACLKX pin.
1 AHCLKX is inverted before programmable bit
clock divider. In the special case where
the transmit bit clock (ACLKX) is
internally generated and the programmable
bit clock divider is set to divide-by-1
(CLKXDIV = 0 in ACLKXCTL), AHCLKX is
directly passed through to the ACLKX pin. |
| 13:12 | RESERVED103 | R | 0h | |
| 11:0 | HCLKXDIV | R/W | 0h | Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX. 0 Divide-by-1.
1 Divide-by-2.
2 Divide-by-3 to divide-by-4096 from 2h to
FFFh. |