SPRUJC6 User guide | 德州仪器 TI.com.cn

SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

2.2.27.1 MCASP_ACLKXCTL Register (Offset = B0h) [reset = 60h]

The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator.

Table 14-11141 Instance Table

Figure 14-5520 MCASP_ACLKXCTL Name Register

Table 14-11142 MCASP_ACLKXCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:21	RESERVED102	R/W	0h
20	BUSY	R/W	0h	Status: logical OR of DIVBUSY, ADJBUSY
19	DIVBUSY	R/W	0h	Status: divide ratio change in progress
18	ADJBUSY	R/W	0h	Status: one-shot adjustment in progress
17:16	CLKXADJ	W	0h	CLKXDIV one-shot adjustment
15:8	RESERVED101	R/W	0h
7	CLKXP	R/W	0h	Transmit bitstream clock polarity select bit. 0 Rising edge. External receiver samples data on the falling edge of the serial clock, so the transmitter must shift data out on the rising edge of the serial clock. 1 Falling edge. External receiver samples data on the rising edge of the serial clock, so the transmitter must shift data out on the falling edge of the serial clock.
6	ASYNC	R/W	1h	Transmit/receive operation asynchronous enable bit. 0 Synchronous. Transmit clock and frame sync provides the source for both the transmit and receive sections. 1 Asynchronous. Separate clock and frame sync used by transmit and receive sections.
5	CLKXM	R/W	1h	Transmit bit clock source bit. 0 External transmit clock source from ACLKX pin. 1 Internal transmit clock source from output of programmable bit clock divider.
4:0	CLKXDIV	R/W	0h	Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX. 0 Divide-by-1. 1 Divide-by-2. 2 Divide-by-3 to divide-by-32 from 2h to 1Fh.