SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes a new interrupt request to be generated.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0080h |
| MCASP1 | 02B1 0080h |
| MCASP2 | 02B2 0080h |
| MCASP3 | 02B3 0080h |
| MCASP4 | 02B4 0080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED91 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED91 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED91 | RERR | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RDMAERR | RSTAFRM | RDATA | RLAST | RTDMSLOT | RCKFAIL | RSYNCERR | ROVRN |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED91 | R | 0h | |
| 8 | RERR | R/W | 0h | RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR. Allows a single bit to be checked to determine if a receiver error interrupt has occurred. 0 No errors have occurred. 1 An error has occurred. |
| 7 | RDMAERR | R/W1TC | 0h | Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the data port in a given time slot than were programmed as receivers. Causes a receive interrupt [RINT], if this bit is set and RDMAERR in RINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 to this bit has no effect. 0 Receive DMA error did not occur. 1 Receive DMA error did occur. |
| 6 | RSTAFRM | R/W1TC | 0h | Receive start of frame flag. Causes a receive interrupt [RINT], if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 to this bit has no effect. 0 No new receive frame sync (AFSR) is
detected.
1 A new receive frame sync (AFSR) is
detected. |
| 5 | RDATA | R/W1TC | 0h | Receive data ready flag. Causes a receive interrupt [RINT], if this bit is set and RDATA in RINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 to this bit has no effect. 0 No new data in RBUF.
1 Data is transferred from XRSR to RBUF and
ready to be serviced by the CPU or DMA.
When RDATA is set, it always causes a DMA
event (AREVT). |
| 4 | RLAST | R/W1TC | 0h | Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. Causes a receive interrupt [RINT], if this bit is set and RLAST in RINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 to this bit has no effect. 0 Current slot is not the last slot in a
frame.
1 Current slot is the last slot in a frame.
RDATA is also set. |
| 3 | RTDMSLOT | R | 0h | Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd. 0 Current TDM time slot is odd. 1 Current TDM time slot is even. |
| 2 | RCKFAIL | R/W1TC | 0h | Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. Causes a receive interrupt [RINT], if this bit is set and RCKFAIL in RINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 to this bit has no effect. 0 Receive clock failure did not occur. 1 Receive clock failure did occur. |
| 1 | RSYNCERR | R/W1TC | 0h | Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync [AFSR] occurs before it is expected. Causes a receive interrupt [RINT], if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 to this bit has no effect. 0 Unexpected receive frame sync did not
occur.
1 Unexpected receive frame sync did occur. |
| 0 | ROVRN | R/W1TC | 0h | Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt [RINT], if this bit is set and ROVRN in RINTCTL is set. This bit is cleared by Writing a 1 to this bit. Writing a 0 to this bit has no effect. 0 Receiver overrun did not occur. 1 Receiver overrun did occur. |