SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates RINT. See the RSTAT register for a description of the interrupt conditions.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 007Ch |
| MCASP1 | 02B1 007Ch |
| MCASP2 | 02B2 007Ch |
| MCASP3 | 02B3 007Ch |
| MCASP4 | 02B4 007Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED90 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED90 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED90 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSTAFRM | RESERVED89 | RDATA | RLAST | RDMAERR | RCKFAIL | RSYNCERR | ROVRN |
| R/W | R | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED90 | R | 0h | |
| 7 | RSTAFRM | R/W | 0h | Receive start of frame interrupt enable bit. 0 Interrupt is disabled. A receive start of
frame interrupt does not generate a McASP
receive interrupt (RINT).
1 Interrupt is enabled. A receive start of
frame interrupt generates a McASP receive
interrupt (RINT). |
| 6 | RESERVED89 | R | 0h | |
| 5 | RDATA | R/W | 0h | Receive data ready interrupt enable bit. 0 Interrupt is disabled. A receive data ready
interrupt does not generate a McASP receive
interrupt (RINT).
1 Interrupt is enabled. A receive data ready
interrupt generates a McASP receive
interrupt (RINT). |
| 4 | RLAST | R/W | 0h | Receive last slot interrupt enable bit. 0 Interrupt is disabled. A receive last slot
interrupt does not generate a McASP receive
interrupt (RINT).
1 Interrupt is enabled. A receive last slot
interrupt generates a McASP receive
interrupt (RINT). |
| 3 | RDMAERR | R/W | 0h | Receive DMA error interrupt enable bit. 0 Interrupt is disabled. A receive DMA error
interrupt does not generate a McASP receive
interrupt (RINT).
1 Interrupt is enabled. A receive DMA error
interrupt generates a McASP receive
interrupt (RINT). |
| 2 | RCKFAIL | R/W | 0h | Receive clock failure interrupt enable bit. 0 Interrupt is disabled. A receive clock
failure interrupt does not generate a McASP
receive interrupt (RINT).
1 Interrupt is enabled. A receive clock
failure interrupt generates a McASP receive
interrupt (RINT). |
| 1 | RSYNCERR | R/W | 0h | Unexpected receive frame sync interrupt enable bit. 0 Interrupt is disabled. An unexpected
receive frame sync interrupt does not
generate a McASP receive interrupt (RINT).
1 Interrupt is enabled. An unexpected receive
frame sync interrupt generates a McASP
receive interrupt (RINT). |
| 0 | ROVRN | R/W | 0h | Receiver overrun interrupt enable bit. 0 Interrupt is disabled. A receiver overrun
interrupt does not generate a McASP receive
interrupt (RINT).
1 Interrupt is enabled. A receiver overrun
interrupt generates a McASP receive
interrupt (RINT). |