SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency controller clock (AHCLKR) and the receive clock generator.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0074h |
| MCASP1 | 02B1 0074h |
| MCASP2 | 02B2 0074h |
| MCASP3 | 02B3 0074h |
| MCASP4 | 02B4 0074h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED88 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED88 | BUSY | DIVBUSY | ADJBUSY | HCLKRADJ | |||
| R/W | R/W | R/W | R/W | W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HCLKRM | HCLKRP | RESERVED87 | HCLKRDIV | ||||
| R/W | R/W | R | R/W | ||||
| 1h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HCLKRDIV | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:21 | RESERVED88 | R/W | 0h | |
| 20 | BUSY | R/W | 0h | Status: logical OR of DIVBUSY, ADJBUSY |
| 19 | DIVBUSY | R/W | 0h | Status: divide ratio change in progress? |
| 18 | ADJBUSY | R/W | 0h | Status: one-shot adjustment in progress? |
| 17:16 | HCLKRADJ | W | 0h | HCLKRDIV one-shot adjustment |
| 15 | HCLKRM | R/W | 1h | Receive high-frequency clock source bit. 0 External receive high-frequency clock
source from AHCLKR pin.
1 Internal receive high-frequency clock
source from output of programmable high
clock divider. |
| 14 | HCLKRP | R/W | 0h | Receive bitstream high-frequency clock polarity select bit. 0 AHCLKR is not inverted before programmable
bit clock divider. In the special case
where the receive bit clock (ACLKR) is
internally generated and the programmable
bit clock divider is set to divide-by-1
(CLKRDIV = 0 in ACLKRCTL), AHCLKR is
directly passed through to the ACLKR pin.
1 AHCLKR is inverted before programmable bit
clock divider. In the special case where
the receive bit clock (ACLKR) is internally
generated and the programmable bit clock
divider is set to divide-by-1 (CLKRDIV = 0
in ACLKRCTL), AHCLKR is directly passed
through to the ACLKR pin. |
| 13:12 | RESERVED87 | R | 0h | |
| 11:0 | HCLKRDIV | R/W | 0h | Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR. 0 Divide-by-1.
1 Divide-by-2.
2 Divide-by-3 to divide-by-4096 from 2h to
FFFh. |