SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The DIT mode control register (DITCTL) controls DIT operations of the McASP.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0050h |
| MCASP1 | 02B1 0050h |
| MCASP2 | 02B2 0050h |
| MCASP3 | 02B3 0050h |
| MCASP4 | 02B4 0050h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED77 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED77 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED77 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED77 | VB | VA | RESERVED76 | DITEN | |||
| R | R/W | R/W | R | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED77 | R | 0h | |
| 3 | VB | R/W | 0h | Valid bit for odd time slots [DIT right subframe]. 0 V bit is 0 during odd DIT subframes. 1 V bit is 1 during odd DIT subframes. |
| 2 | VA | R/W | 0h | Valid bit for even time slots [DIT left subframe]. 0 V bit is 0 during even DIT subframes. 1 V bit is 1 during even DIT subframes. |
| 1 | RESERVED76 | R | 0h | |
| 0 | DITEN | R/W | 0h | DIT mode enable bit. DITEN should only be changed while the XSMRST bit in GBLCTL is in reset [and for startup, XSRCLR also in reset]. However, it is not necessary to reset the XCLKRST or XHCLKRST bits in GBLCTL to change DITEN. 0 DIT mode is disabled. Transmitter operates
in TDM or burst mode.
1 DIT mode is enabled. Transmitter operates
in DIT encoded mode. |