SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read, regardless of the state of PFUNC and PDIR. The value after reset for registers 1 through 15 and 24 through 31 depends on how the pins are being driven. CAUTION: Writing a value other than 0 to reserved bits in this register may cause improper device operation.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 001Ch |
| MCASP1 | 02B1 001Ch |
| MCASP2 | 02B2 001Ch |
| MCASP3 | 02B3 001Ch |
| MCASP4 | 02B4 001Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| AFSR | AHCLKR | ACLKR | AFSX | AHCLKX | ACLKX | AMUTE | RESERVED70 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED70 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED70 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED70 | AXR | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | AFSR | R/W | 0h | Logic level on AFSR pin. 0 Pin is logic low. 1 Pin is logic high. |
| 30 | AHCLKR | R/W | 0h | Logic level on AHCLKR pin. 0 Pin is logic low. 1 Pin is logic high. |
| 29 | ACLKR | R/W | 0h | Logic level on ACLKR pin. 0 Pin is logic low. 1 Pin is logic high. |
| 28 | AFSX | R/W | 0h | Logic level on AFSX pin. 0 Pin is logic low. 1 Pin is logic high. |
| 27 | AHCLKX | R/W | 0h | Logic level on AHCLKX pin. 0 Pin is logic low. 1 Pin is logic high. |
| 26 | ACLKX | R/W | 0h | Logic level on ACLKX pin. 0 Pin is logic low. 1 Pin is logic high. |
| 25 | AMUTE | R/W | 0h | Logic level on AMUTE pin. 0 Pin is logic low. 1 Pin is logic high. |
| 24:4 | RESERVED70 | R | 0h | |
| 3:0 | AXR | R/W | 0h | Logic level on AXR[n] pin. 0 Pin is logic low. 1 Pin is logic high. |