SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The pin data output register (PDOUT) holds a value for data out at all times, and may be read back at all times. The value held by PDOUT is not affected by writing to PDIR and PFUNC. However, the data value in PDOUT is driven out onto the McASP pin only if the corresponding bit in PFUNC is set to 1 (GPIO function) and the corresponding bit in PDIR is set to 1 (output). When reading data, returns the corresponding bit value in PDOUT[n], does not return input from I/O pin; when writing data, writes to the corresponding PDOUT[n] bit. PDOUT has these aliases or alternate addresses: PDSET When written to at this address, writing a 1 to a bit in PDSET sets the corresponding bit in PDOUT to 1; writing a 0 has no effect and keeps the bits in PDOUT unchanged. PDCLR When written to at this address, writing a 1 to a bit in PDCLR clears the corresponding bit in PDOUT to 0; writing a 0 has no effect and keeps the bits in PDOUT unchanged. There is only one set of data out bits, PDOUT[31-0]. The other registers, PDSET and PDCLR, are just different addresses for the same control bits, with different behaviors during writes. CAUTION: Writing a value other than 0 to reserved bits in this register may cause improper device operation.
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 0018h |
| MCASP1 | 02B1 0018h |
| MCASP2 | 02B2 0018h |
| MCASP3 | 02B3 0018h |
| MCASP4 | 02B4 0018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| AFSR | AHCLKR | ACLKR | AFSX | AHCLKX | ACLKX | AMUTE | RESERVED69 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED69 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED69 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED69 | AXR | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | AFSR | R/W | 0h | Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |
| 30 | AHCLKR | R/W | 0h | Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |
| 29 | ACLKR | R/W | 0h | Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |
| 28 | AFSX | R/W | 0h | Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |
| 27 | AHCLKX | R/W | 0h | Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |
| 26 | ACLKX | R/W | 0h | Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |
| 25 | AMUTE | R/W | 0h | Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |
| 24:4 | RESERVED69 | R | 0h | |
| 3:0 | AXR | R/W | 0h | Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1. 0 Pin drives low. 1 Pin drives high. |