SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Control Register contains general control bits for the MCANSS
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| Instance Name | Physical Address |
|---|---|
| MCAN0 | 2070 0004h |
| MCAN1 | 2071 0004h |
| MCAN2 | 2072 0004h |
| MCAN3 | 2073 0004h |
| MCAN4 | 2074 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EXT_TS_CNTR_EN | AUTOWAKEUP | WAKEUPREQEN | DBGSUSP_FREE | RESERVED | ||
| NONE | R/W | R/W | R/W | R/W | NONE | ||
| 0h | 0h | 0h | 0h | 1h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:7 | RESERVED | NONE | 0h | Reserved |
| 6 | EXT_TS_CNTR_EN | R/W | 0h | External Timestamp Counter Enable Reset Source: hsrst_n |
| 5 | AUTOWAKEUP | R/W | 0h | Automatic Wakeup Enable Reset Source: hsrst_n |
| 4 | WAKEUPREQEN | R/W | 0h | Wakeup Request Enable Reset Source: hsrst_n |
| 3 | DBGSUSP_FREE | R/W | 1h | Debug Suspend 0h Honor debug suspend 1h Disregard debug suspend |
| 2:0 | RESERVED | NONE | 0h | Reserved |