SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The interrupt status register has the status for each event that may be responsible for the generation of an interrupt to the corresponding user combined with the corresponding MASK information. Software may also write 1 to a given bit to clear this bit. However, if the hardware still has pending, enabled events, the interrupt will fire again in two cycles. Write 0 has no effect.
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| Instance Name | Physical Address |
|---|---|
| MAILBOX0_MAILBOX_CLUSTER_2 | 2902 0104h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NOTFULLSTATUSMB15 | NEWMSGSTATUSMB15 | NOTFULLSTATUSMB14 | NEWMSGSTATUSMB14 | NOTFULLSTATUSMB13 | NEWMSGSTATUSMB13 | NOTFULLSTATUSMB12 | NEWMSGSTATUSMB12 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NOTFULLSTATUSMB11 | NEWMSGSTATUSMB11 | NOTFULLSTATUSMB10 | NEWMSGSTATUSMB10 | NOTFULLSTATUSMB9 | NEWMSGSTATUSMB9 | NOTFULLSTATUSMB8 | NEWMSGSTATUSMB8 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NOTFULLSTATUSMB7 | NEWMSGSTATUSMB7 | NOTFULLSTATUSMB6 | NEWMSGSTATUSMB6 | NOTFULLSTATUSMB5 | NEWMSGSTATUSMB5 | NOTFULLSTATUSMB4 | NEWMSGSTATUSMB4 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NOTFULLSTATUSMB3 | NEWMSGSTATUSMB3 | NOTFULLSTATUSMB2 | NEWMSGSTATUSMB2 | NOTFULLSTATUSMB1 | NEWMSGSTATUSMB1 | NOTFULLSTATUSMB0 | NEWMSGSTATUSMB0 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | NOTFULLSTATUSMB15 | R/W | 0h | 1 if Mailbox 15 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 30 | NEWMSGSTATUSMB15 | R/W | 0h | 1 if there are messages present in Mailbox 15 and this interrupt bit is enabled Reset Source: rst_n |
| 29 | NOTFULLSTATUSMB14 | R/W | 0h | 1 if Mailbox 14 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 28 | NEWMSGSTATUSMB14 | R/W | 0h | 1 if there are messages present in Mailbox 14 and this interrupt bit is enabled Reset Source: rst_n |
| 27 | NOTFULLSTATUSMB13 | R/W | 0h | 1 if Mailbox 13 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 26 | NEWMSGSTATUSMB13 | R/W | 0h | 1 if there are messages present in Mailbox 13 and this interrupt bit is enabled Reset Source: rst_n |
| 25 | NOTFULLSTATUSMB12 | R/W | 0h | 1 if Mailbox 12 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 24 | NEWMSGSTATUSMB12 | R/W | 0h | 1 if there are messages present in Mailbox 12 and this interrupt bit is enabled Reset Source: rst_n |
| 23 | NOTFULLSTATUSMB11 | R/W | 0h | 1 if Mailbox 11 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 22 | NEWMSGSTATUSMB11 | R/W | 0h | 1 if there are messages present in Mailbox 11 and this interrupt bit is enabled Reset Source: rst_n |
| 21 | NOTFULLSTATUSMB10 | R/W | 0h | 1 if Mailbox 10 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 20 | NEWMSGSTATUSMB10 | R/W | 0h | 1 if there are messages present in Mailbox 10 and this interrupt bit is enabled Reset Source: rst_n |
| 19 | NOTFULLSTATUSMB9 | R/W | 0h | 1 if Mailbox 9 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 18 | NEWMSGSTATUSMB9 | R/W | 0h | 1 if there are messages present in Mailbox 9 and this interrupt bit is enabled Reset Source: rst_n |
| 17 | NOTFULLSTATUSMB8 | R/W | 0h | 1 if Mailbox 8 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 16 | NEWMSGSTATUSMB8 | R/W | 0h | 1 if there are messages present in Mailbox 8 and this interrupt bit is enabled Reset Source: rst_n |
| 15 | NOTFULLSTATUSMB7 | R/W | 0h | 1 if Mailbox 7 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 14 | NEWMSGSTATUSMB7 | R/W | 0h | 1 if there are messages present in Mailbox 7 and this interrupt bit is enabled Reset Source: rst_n |
| 13 | NOTFULLSTATUSMB6 | R/W | 0h | 1 if Mailbox 6 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 12 | NEWMSGSTATUSMB6 | R/W | 0h | 1 if there are messages present in Mailbox 6 and this interrupt bit is enabled Reset Source: rst_n |
| 11 | NOTFULLSTATUSMB5 | R/W | 0h | 1 if Mailbox 5 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 10 | NEWMSGSTATUSMB5 | R/W | 0h | 1 if there are messages present in Mailbox 5 and this interrupt bit is enabled Reset Source: rst_n |
| 9 | NOTFULLSTATUSMB4 | R/W | 0h | 1 if Mailbox 4 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 8 | NEWMSGSTATUSMB4 | R/W | 0h | 1 if there are messages present in Mailbox 4 and this interrupt bit is enabled Reset Source: rst_n |
| 7 | NOTFULLSTATUSMB3 | R/W | 0h | 1 if Mailbox 3 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 6 | NEWMSGSTATUSMB3 | R/W | 0h | 1 if there are messages present in Mailbox 3 and this interrupt bit is enabled Reset Source: rst_n |
| 5 | NOTFULLSTATUSMB2 | R/W | 0h | 1 if Mailbox 2 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 4 | NEWMSGSTATUSMB2 | R/W | 0h | 1 if there are messages present in Mailbox 2 and this interrupt bit is enabled Reset Source: rst_n |
| 3 | NOTFULLSTATUSMB1 | R/W | 0h | 1 if Mailbox 1 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 2 | NEWMSGSTATUSMB1 | R/W | 0h | 1 if there are messages present in Mailbox 1 and this interrupt bit is enabled Reset Source: rst_n |
| 1 | NOTFULLSTATUSMB0 | R/W | 0h | 1 if Mailbox 0 is not full and this interrupt bit is enabled Reset Source: rst_n |
| 0 | NEWMSGSTATUSMB0 | R/W | 0h | 1 if there are messages present in Mailbox 0 and this interrupt bit is enabled Reset Source: rst_n |