SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Enable Clear Register 0
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| Instance Name | Physical Address |
|---|---|
| WKUP_VTM0 | 00B0 20C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | ECCAGG_ENABLE_CLR | |||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3 | K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_k3vtm_n16ffc_cfg_cbass_cfg_scr_scr_edc_ctrl_busecc_pend |
| 2 | K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_VBUSP_BRIDGE_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_cfg_cbass_vbusp_p2p_bridge_vbusp_bridge_busecc_pend |
| 1 | K3VTM_N16FFC_MMR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for k3vtm_n16ffc_mmr_edc_ctrl_busecc_pend |
| 0 | ECCAGG_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for eccagg_pend |