SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Temperature Sensor Band-gap Status register for sensor j.
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| Instance Name | Physical Address |
|---|---|
| WKUP_VTM0 | 00B0 0308h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | VD_MAP | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MAXT_OUTRG_ALERT | LT_TH0_ALERT | GT_TH2_ALERT | GT_TH1_ALERT | EOC_FC_UPDATE | DATA_VALID | DATA_OUT | |
| R | R | R | R | R | R | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DATA_OUT | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | VD_MAP | R | 0h | Indicates the core voltage domain placement of the temp sensor. Device specific field. This field indicates in which core voltage domain, cVD, has been physically placed the temp-monitor. Valid values: 0x0 to 0xE where: 0x0 = VD_RTC, not present is some SOCs, 0x1 = VD_WKUP, 0x2 = VD_MCU, 0x3 = VD_CORE, not present is some SOCs, 0x4-0xE = Mapping varies between SOCs, 0xF = not implemented. Reset value is a VTM tieoff at POR, d_VTM_TMPSENS[j]_STAT_vd_map_ipcfg. Reset Source: mod_por_rst_n |
| 15 | MAXT_OUTRG_ALERT | R | 0h | This bit will be driven to a level 1 for a given temperature monitor if it has its corresponding bit maxt_outrg_en = 1, and the temperature reading is reporting to be outside the max temperature supported, temp > programmed value. The level of this signal is a reflection, with some clock delays, of the temperature code reading. This is NOT an sticky bit. Reset value is POR only. Reset Source: mod_por_rst_n |
| 14 | LT_TH0_ALERT | R | 0h | This field reflects the status of the lt_th0_alert comparator result during continuous mode. The control MMR field lt_th0_en = 1 is required for this field to become 1. Reset value is at POR or clrz. Reset Source: mod_por_rst_n |
| 13 | GT_TH2_ALERT | R | 0h | This field reflects the status of the gt_th2_alert comparator result during continuous mode. The control MMR field gt_th2_en = 1 is required for this field to become 1. Reset value is at POR or clrz. Reset Source: mod_por_rst_n |
| 12 | GT_TH1_ALERT | R | 0h | This field reflects the status of the gt_th1_alert comparator result during continuous mode. The control MMR field gt_th1_en = 1 is required for this field to become 1. Reset value is at POR or clrz. Reset Source: mod_por_rst_n |
| 11 | EOC_FC_UPDATE | R | 0h | First time end of conversion. This field is reset to 0 every time VTM.por_rst_n or VTM_TMPSENS[j]_CTRL.clrz are active, or when continuous mode is deasserted. This bit will be set to 1 after the first time after reset release that data_valid transitions from 0 to 1, and remain at 1 until next time either of por_rst_n or VTM_TMPSENS[j]_CTRL.clrz are active, or when continuous mode is deasserted. Reset value is at POR or VTM_TMPSENS[j]_CTRL.clrz, or continuous mode deassertion. Reset Source: mod_por_rst_n |
| 10 | DATA_VALID | R | 0h | Data_valid signal value from sensor: ADC End of Conversion. End of conversion indicated by 0 to 1 transition. When high data_out(9:0) out of the temp-monitor is valid. This field doesn't reflect the instantaneous output from the temp-monitor. This field gets latched/updated in this VTM register when the data_valid value from temp-monitor toggles. Note the data_valid sensor output is asserted for only a short time window (on the order of a few clock cycles). Reset value is at POR or VTM_TMPSENS[j]_CTRL.clrz. Reset Source: mod_por_rst_n |
| 9:0 | DATA_OUT | R | 0h | Data_out signal value from sensor: Temperature data from the ADC in monitor. Valid after VTM_TMPSENS[j]_STAT.eoc_fc_update = 1. This value will be latched in this VTM register every time monitor output data_valid transitions from 0 to 1 (specifically one vbus cycle after data_valid asserts). Reset value is POR only. Reset Source: mod_por_rst_n |