SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Voltage domain a information register. The default reset values will not be necessarily overwritten. The write capability in the MMR is for having the option to debug and have software driven adjustments if necessary.
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| Instance Name | Physical Address |
|---|---|
| WKUP_VTM0 | 00B0 0100h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | AVS0_SUP | VD_MAP | |||||
| NONE | R/W | R | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED | NONE | 0h | Reserved |
| 12 | AVS0_SUP | R/W | 0h | Indicates VD0 AVS class0 support. Indicates if the cVD associated with this VTM's VD MMR supports AVS-Class0: 0: No AVS-Class0. 1: Supports-AVS-Class0. Reset value is from e-fuse at module (POR) reset, efuse_vd[j]_avs_sup. Reset Source: mod_g_rst_n |
| 11:8 | VD_MAP | R | 0h | Indicates the core voltage domain mapping of VTM VD. Device specific field. This field indicates to which SOC cVD is this VD of this VTM map to. Valid values: 0x0 to 0xE where: 0x0 = VD_RTC, not present is some SOCs, 0x1 = VD_WKUP, 0x2 = VD_MCU, 0x3 = VD_CORE, not present is some SOCs, 0x4-0xE = Mapping varies between SOCs, 0xF = not implemented. Reset value is a VTM tieoff, d_vd[j]_vd_map_ipcfg (technically a direct connection, not latched, so reset agnostic). Reset Source: mod_g_rst_n |
| 7:0 | RESERVED | NONE | 0h | Reserved |