SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RAM Info Mask Register
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| Instance Name | Physical Address |
|---|---|
| PBIST0 | 0039 01C8h |
| PBIST1 | 003A 01C8h |
| PBIST2 | 003B 01C8h |
| PBIST3 | 003C 01C8h |
| PBIST4 | 003D 01C8h |
| PBIST5 | 003E 01C8h |
| PBIST6 | 003F 01C8h |
| PBIST7 | 0034 01C8h |
| PBIST8 | 0035 01C8h |
| WKUP_PBIST0 | 2B50 01C8h |
| WKUP_PBIST1 | 2B50 11C8h |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 48 |
| U3 | |||||||
| R/W | |||||||
| FFh | |||||||
| 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
| U2 | |||||||
| R/W | |||||||
| FFh | |||||||
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| U1 | |||||||
| R/W | |||||||
| FFh | |||||||
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| U0 | |||||||
| R/W | |||||||
| FFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| L1 | |||||||
| R/W | |||||||
| FFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| L0 | |||||||
| R/W | |||||||
| FFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:56 | U3 | R/W | FFh | RAM Info Mask Upper 3 (RINFOU3) Reset Source: mod_g_rst_n |
| 55:48 | U2 | R/W | FFh | RAM Info Mask Upper 2 (RINFOU2) Reset Source: mod_g_rst_n |
| 47:40 | U1 | R/W | FFh | RAM Info Mask Upper 1 (RINFOU1) Reset Source: mod_g_rst_n |
| 39:32 | U0 | R/W | FFh | RAM Info Mask Upper 0 (RINFOU0) Reset Source: mod_g_rst_n |
| 31:24 | L3 | R/W | FFh | RAM Info Mask Lower 3 (RINFOL3) Reset Source: mod_g_rst_n |
| 23:16 | L2 | R/W | FFh | RAM Info Mask Lower 2 (RINFOL2) Reset Source: mod_g_rst_n |
| 15:8 | L1 | R/W | FFh | RAM Info Mask Lower 1 (RINFOL1) Reset Source: mod_g_rst_n |
| 7:0 | L0 | R/W | FFh | RAM Info Mask Lower 0 (RINFOL0) Reset Source: mod_g_rst_n |