SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the enable interrupt status as defined in HL0.8 for the Output Group interrupts. The FIFO interrupt for each group is configured in the control register for the group. This register is used to read and set the interrupt source enables. The enable bit is active high and a 1 indicates the source is enabled to interrupt the processor(s), while a 0 indicates the source will not interrupt the processor(s).
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 005Ch |
| AASRC1 | 02D4 005Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GROUP_3_OUTPUT_FIFO_THRESHOLD_ENABLE | GROUP_2_OUTPUT_FIFO_THRESHOLD_ENABLE | GROUP_1_OUTPUT_FIFO_THRESHOLD_ENABLE | GROUP_0_OUTPUT_FIFO_THRESHOLD_ENABLE | |||
| R | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | R | 0h | Always read as 0 |
| 3 | GROUP_3_OUTPUT_FIFO_THRESHOLD_ENABLE | R/W1TS | 0h | Group 3 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will set enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 2 | GROUP_2_OUTPUT_FIFO_THRESHOLD_ENABLE | R/W1TS | 0h | Group 2 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will set enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 1 | GROUP_1_OUTPUT_FIFO_THRESHOLD_ENABLE | R/W1TS | 0h | Group 1 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will set enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 0 | GROUP_0_OUTPUT_FIFO_THRESHOLD_ENABLE | R/W1TS | 0h | Group 10 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will set enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |