SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the raw interrupt status as defined in HL0.8 for the Input Group interrupts. The FIFO interrupt for each group is configured in the control register for the group. A read of the Interrupt Status Raw / Set Register returns the current pending status of the interrupt sources with no regard to any enable settings. A write to this register sets the interrupt pending status of each interrupt source whose corresponding bit is 1 in the value written. Note that reading this register immediately after writing to it would reflect old value instead of the written value; wait for 2 system clock cycles after writing to read written value.
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0044h |
| AASRC1 | 02D4 0044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GROUP_3_INPUT_FIFO_THRESHOLD_RAW | GROUP_2_INPUT_FIFO_THRESHOLD_RAW | GROUP_1_INPUT_FIFO_THRESHOLD_RAW | GROUP_0_INPUT_FIFO_THRESHOLD_RAW | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | R | 0h | Always read as 0 |
| 3 | GROUP_3_INPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Group 3 Input FIFO Threshold Interrupt Read indicates raw status. This fires when all the Input FIFOs for this Group is below the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 2 | GROUP_2_INPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Group 2 Input FIFO Threshold Interrupt Read indicates raw status. This fires when all the the Input FIFOs for this Group is below the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 1 | GROUP_1_INPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Group 1 Input FIFO Threshold Interrupt Read indicates raw status. This fires when all the Input FIFOs for this Group is below the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |
| 0 | GROUP_0_INPUT_FIFO_THRESHOLD_RAW | R/W | 0h | Group 0 Input FIFO Threshold Interrupt Read indicates raw status. This fires when all the Input FIFOs for this Group is below the level set in the Configuration register. Writing 1 will set status and Writing 0 has no effect 0 Status inactive 1 Status active |