SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the enable interrupt status as defined in HL0.8 for the Output FIFO interrupts. The FIFO interrupt for each Channel is configured in the control register for the Channel. A read of the Interrupt Enable Clr register returns the current enable bits for the interrupt sources. A write to this register sets the enable to 0 for any source whose corresponding bit is 1 in the value written
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0040h |
| AASRC1 | 02D4 0040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CHANNEL_15_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_14_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_13_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_12_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_11_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_10_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_9_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_8_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHANNEL_7_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_6_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_5_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_4_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_3_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_2_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_1_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | CHANNEL_0_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | R | 0h | Always read as 0 |
| 15 | CHANNEL_15_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 15 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 14 | CHANNEL_14_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 14 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 13 | CHANNEL_13_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 13 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 12 | CHANNEL_12_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 12 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 11 | CHANNEL_11_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 11 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 10 | CHANNEL_10_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 10 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 9 | CHANNEL_9_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 9 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 8 | CHANNEL_8_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 8 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 7 | CHANNEL_7_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 7 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 6 | CHANNEL_6_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 6 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 5 | CHANNEL_5_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 5 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 4 | CHANNEL_4_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 4 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 3 | CHANNEL_3_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 3 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 2 | CHANNEL_2_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 2 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 1 | CHANNEL_1_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 1 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 0 | CHANNEL_0_OUTPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Channel 0 Output FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |