SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
AASRC SYSCONFIG
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0010h |
| AASRC1 | 02D4 0010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DATA_FORMAT_DISABLE | SOFTRESET | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | R | 0h | Always read as 0 |
| 1 | DATA_FORMAT_DISABLE | R/W | 0h | If this bit is set, data formatting needs to be done outside 0 Data formatting enabled 1 Data formatting disabled |
| 0 | SOFTRESET | R/W | 0h | Write 1'b1 for reset assertion and 1'b0 for reset de-assertion 0 Reset not asserted 1 Reset is asserted |