SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is set to all 0s.
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| Instance Name | Physical Address |
|---|---|
| WKUP_GTC0 | 00AB 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CNTTIDR_FRAME7 | CNTTIDR_FRAME6 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CNTTIDR_FRAME5 | CNTTIDR_FRAME4 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CNTTIDR_FRAME3 | CNTTIDR_FRAME2 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CNTTIDR_FRAME1 | CNTTIDR_FRAME0 | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | CNTTIDR_FRAME7 | R | 0h | Indicates the features of timer frame7. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |
| 27:24 | CNTTIDR_FRAME6 | R | 0h | Indicates the features of timer frame6. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |
| 23:20 | CNTTIDR_FRAME5 | R | 0h | Indicates the features of timer frame5. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |
| 19:16 | CNTTIDR_FRAME4 | R | 0h | Indicates the features of timer frame4. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |
| 15:12 | CNTTIDR_FRAME3 | R | 0h | Indicates the features of timer frame3. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |
| 11:8 | CNTTIDR_FRAME2 | R | 0h | Indicates the features of timer frame2. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |
| 7:4 | CNTTIDR_FRAME1 | R | 0h | Indicates the features of timer frame1. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |
| 3:0 | CNTTIDR_FRAME0 | R | 0h | Indicates the features of timer frame0. Each 4 bit field has the following meaning: Reset Source: mod_por_rst_n |