SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enables the System Counter and controls counter operation during debug
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| Instance Name | Physical Address |
|---|---|
| WKUP_GTC0 | 00A9 0000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CNTCR_FCREQ | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CNTCR_FCREQ | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CNTCR_FCREQ | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CNTCR_HDBG | CNTCR_EN | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | CNTCR_FCREQ | R | 0h | Frequency Change Request Reset Source: mod_por_rst_n |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1 | CNTCR_HDBG | R/W | 0h | Halt on Debug Reset Source: mod_por_rst_n |
| 0 | CNTCR_EN | R/W | 0h | Enable System Counter Reset Source: mod_por_rst_n |