SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Bank Interrupt Status Register
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| Instance Name | Physical Address |
|---|---|
| GPIO0 | 0060 0084h |
| GPIO1 | 0060 1084h |
| MCU_GPIO0 | 0420 1084h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| STAT5 | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| STAT5 | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| STAT4 | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STAT4 | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | STAT5 | R/W1TC | 0h | Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status. Reset Source: mod_g_srst_n |
| 15:0 | STAT4 | R/W1TC | 0h | Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status. Reset Source: mod_g_srst_n |