SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
FOTA general purpose 1 register. M8051EW can write to this register to pass information to SOC CPU through ESFR space. Interpretation for this register is software defined and can be made context dependent if required.
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC6 0014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| VAL3 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| VAL2 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| VAL1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VAL0 | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | VAL3 | R | 0h | General purpose 1 register val3. Reset Source: vbus_mod_g_rst_n |
| 23:16 | VAL2 | R | 0h | General purpose 1 register val2. Reset Source: vbus_mod_g_rst_n |
| 15:8 | VAL1 | R | 0h | General purpose 1 register val1. Reset Source: vbus_mod_g_rst_n |
| 7:0 | VAL0 | R | 0h | General purpose 1 register val0. Reset Source: vbus_mod_g_rst_n |