SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to start M8051EW firmware.
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC6 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GO | ||||||
| NONE | R/W1TS | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | GO | R/W1TS | 0h | SOC CPU sets this bit to indicate to M8051EW firmware that it can start the next FOTA page write. Once go is set, SOC software has to ensure that it is set again only after receiving an interrupt (completion or error) from M8051EW. If this requirement is not followed, it could result in M8051EW firmware repeating the FOTA write erroneously. A write to this register causes an indirect write to ESFR space for M8051EW. Firmware polls until ESFR GO bit is set and then starts the FOTA write sequence. This bit is cleared by hardware when the MCU has acknowledged GO through a write to the GO_ACK ESFR bit. Reset Source: vbus_mod_g_rst_n |