SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IRQSTATUS_RAW
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC2 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MAC_ERR | WRT_ERR | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REGION_BV | CTR_WKV | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:12 | MAC_ERR | R/W | 0h | MAC error Reset Source: rst_modg_rst_n |
| 11:8 | WRT_ERR | R/W | 0h | Write error Reset Source: rst_modg_rst_n |
| 7:4 | REGION_BV | R/W | 0h | Region overflow boundary event caused by a burst transaction crossed a start or end of a region Reset Source: rst_modg_rst_n |
| 3:0 | CTR_WKV | R/W | 0h | AES mode 0 enabled region violated Wrt Once Per Wrt Key rule Reset Source: rst_modg_rst_n |