SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CS# Memory Timing Register
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| Instance Name | Physical Address |
|---|---|
| FSS1_HYPERBUS1P0_0 | 0FC3 4030h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RCSHI | WCSHI | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RCSS | WCSS | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RCSH | WCSH | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RFU12 | LTCY | ||||||
| R | R/W | ||||||
| 0h | 1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RCSHI | R/W | 0h | Read Chip Select High Between Operations. This bit indicates CS# high time for read between operations. 0x0 corresponds to 1.5 clock cycle, 0xF corresponds to 16.5 clock cycle. Reset Source: mod_g_rst_n |
| 27:24 | WCSHI | R/W | 0h | Write Chip Select High Between Operations. This bit indicates CS# high time for write between operations. 0x0 corresponds to 1.5 clock cycle, 0xF corresponds to 16.5 clock cycle. Reset Source: mod_g_rst_n |
| 23:20 | RCSS | R/W | 0h | Read Chip Select Setup to next CK rising edge. This bit indicates CS# setup time for read from CS# assertion. 0x0 corresponds to 1 clock cycle, 0xF corresponds to 16 clock cycle. Reset Source: mod_g_rst_n |
| 19:16 | WCSS | R/W | 0h | Write Chip Select Setup to next CK rising edge. This bit indicates CS# setup time for write from CS# assertion. 0x0 corresponds to 1 clock cycle, 0xF corresponds to 16 clock cycle Reset Source: mod_g_rst_n |
| 15:12 | RCSH | R/W | 0h | Read Chip Select Hold after CK falling edge. This bit indicates CS# hold time for read to CS# de-assertion. 0x0 corresponds to 1 clock cycle, 0xF corresponds to 16 clock cycle. Reset Source: mod_g_rst_n |
| 11:8 | WCSH | R/W | 0h | Write Chip Select Hold after CK falling edge. This bit indicates CS# hold time for write to CS# de-assertion. 0x0 corresponds to 1 clock cycle, 0xF corresponding to 16 clock cycle Reset Source: mod_g_rst_n |
| 7:4 | RFU12 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 3:0 | LTCY | R/W | 1h | Latency Cycle. Only uses in HyperRAM. This bit indicates initial latency code for read/write access. This bit is ignored when MCRX.DEVTYPE is 0 [HyperFlash]. 0000 - 5 clock latency 0001 - 6 clock latency 0010 - Reserved 1101 - Reserved 1110 - 3 clock latency 1111 - 4 clock latency Reset Source: mod_g_rst_n |