SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
HyperBus Memory Controller IP outputs optional interrupt signal by condition enabled by this register
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| Instance Name | Physical Address |
|---|---|
| FSS1_HYPERBUS1P0_0 | 0FC3 4004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| INTP | RFU4 | ||||||
| R/W | R | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RFU4 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RFU4 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RFU4 | RPCINTE | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | INTP | R/W | 0h | Interrupt Polarity Control. This bit is used to choose the polarity of optional interrupt signal [IENOn].0 -IENOn signal is active low.1 -IENOn signal is active high. [Reversed mode.] Reset Source: mod_g_rst_n |
| 30:1 | RFU4 | R | 0h | This field is reserved for future use Reset Source: mod_g_rst_n |
| 0 | RPCINTE | R/W | 0h | HyperBus Memory Interrupt Enable.0 - Disable interrupt.1 - Enable interrupt by INT# signal of HyperBus memory. Reset Source: mod_g_rst_n |