SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CryptoCfg
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| Instance Name | Physical Address |
|---|---|
| FSS1_FSAS_0 | 0FCA 0018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MASTER_EN_RD | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ERROR_RESP_EN | OTFA_WAIT | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CACHE_ENABLE | CACHE_EVICT_MODE | KEY_SIZE | RD_WRT_OPT | |||
| NONE | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | MASTER_EN_RD | R/W | 0h | This register controls the enabling the functionality of this IP Disabled and Bypass mode active Reset Source: rst_modg_rst_n |
| 30:10 | RESERVED | NONE | 0h | Reserved |
| 9 | ERROR_RESP_EN | R/W | 0h | This register controls the enabling the the ocp error response for mac errors Reset Source: rst_modg_rst_n |
| 8 | OTFA_WAIT | R/W | 0h | This register allows the ability to stop accepting any new transactions from getting accepted and allow the current transactions to complete Reset Source: rst_modg_rst_n |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6 | CACHE_ENABLE | R/W | 0h | MAC cache enable Reset Source: rst_modg_rst_n |
| 5 | CACHE_EVICT_MODE | R/W | 0h | cache evict mode Reset Source: rst_modg_rst_n |
| 4 | KEY_SIZE | R/W | 0h | Key Size, 0 128 Bit 1 256 Bit Reset Source: rst_modg_rst_n |
| 3:0 | RD_WRT_OPT | R/W | 0h | This register defines the static allocation of the AES cores to read transactions. The remainder will be allocated to write transactions Reset Source: rst_modg_rst_n |