SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Ring OrderID Register contains the bus orderid value for the ring memory access.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_RINGACC_0 | 4980 0050h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | REPLACE | ORDERID | |||||
| NONE | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | REPLACE | R/W | 0h | Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source transaction for the destination transaction. 1 = use the orderid MMR field value for the destination transaction. Reset Source: srst_n |
| 3:0 | ORDERID | R/W | 0h | Defines the bus orderid value for this ring or queue. Reset Source: srst_n |