SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Tx Ring Size Register contains the element size and element counts for the ring which is used to hand off pending work for the channel from the Host. A write to this register will reset the associated ring to clear the occupancies and reset the pointers.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_RINGACC_0 | 4980 0048h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| QMODE | RESERVED | ELSIZE | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SIZE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SIZE | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SIZE | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | QMODE | R/W | 0h | Defines the mode for this ring or queue. 0 exposed ring mode for SW direct access
1 messaging mode when all operations are
through bus accesses, allowing multiple
producers or consumers.
2 credentials mode is message mode plus
stores credentials with each message,
requiring the ring size to be doubled to
fit the credentials along with the same
number of elements when using the first 2
modes. Any exposed memory should be
protected by a firewall from unwanted
access. |
| 29:27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | ELSIZE | R/W | 0h | Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED Reset Source: srst_n |
| 23:20 | RESERVED | NONE | 0h | Reserved |
| 19:0 | SIZE | R/W | 0h | Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number. Reset Source: srst_n |