SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register determines how ingress global events from the ingress global event ETL are written out to the two egress global event ETL intefaces. The index of each of the two egress events is stored in this register, which is selected based in the ingress event index value.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_INTAGGR_0 | 4821 0000h + formula |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 48 |
| IRQMODE1 | RESERVED | ||||||
| R/W | NONE | ||||||
| 0h | 0h | ||||||
| 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| GEVIDX1 | |||||||
| R/W | |||||||
| FFFFh | |||||||
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| GEVIDX1 | |||||||
| R/W | |||||||
| FFFFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| GEVIDX0 | |||||||
| R/W | |||||||
| FFFFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GEVIDX0 | |||||||
| R/W | |||||||
| FFFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63 | IRQMODE1 | R/W | 0h | IRQ Mode Flag 1. When set, this register act like a mapper with bitnum in 37:32 and regnum in 46:38. Reset Source: srst_n |
| 62:48 | RESERVED | NONE | 0h | Reserved |
| 47:32 | GEVIDX1 | R/W | FFFFh | Global event index 1. This field specifies the index of the outgoing global event on ETL 1. Set to 0xFFFF to disable. Reset Source: srst_n |
| 31 | IRQMODE0 | R/W | 0h | IRQ Mode Flag 0. When set, this register act like a mapper with bitnum in 5:0 and regnum in 14:6. Reset Source: srst_n |
| 30:16 | RESERVED | NONE | 0h | Reserved |
| 15:0 | GEVIDX0 | R/W | FFFFh | Global event index 0. This field specifies the index of the outgoing global event on ETL 0. Set to 0xFFFF to disable. Reset Source: srst_n |