SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Interrupt Mapping Register controls which of N virtual interrupt source outputs this channels physical interrupt sources will map onto.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_INTAGGR_0 | 4810 0000h + formula |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 48 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| REGNUM | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BITNUM | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:17 | RESERVED | NONE | 0h | Reserved |
| 16:8 | REGNUM | R/W | 0h | Virtual interrupt status register number: this field specifies which of the potential virtual interrupt cause registers the event pending bit will appear in. Reset Source: srst_n |
| 7:6 | RESERVED | NONE | 0h | Reserved |
| 5:0 | BITNUM | R/W | 0h | Virtual interrupt cause register bit number: this field specifies which of the 64 bits in the specified virtual interrupt cause register the event pending bit will appear in. Reset Source: srst_n |