SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Tx Channel Realtime Control Register contains real-time control and status information for the Tx DMA channel. The fields in this register can safely be changed while the channel is in operation.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_BCDMA_0 | 4C00 0000h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TX_ENABLE | TX_TEARDOWN | TX_PAUSE | TX_FORCED_TEARDOWN | RESERVED | |||
| R/W | R/W | R/W | R/W | NONE | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TX_ERROR | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | TX_ENABLE | R/W | 0h | This field enables or disables the channel. Disabling a channel halts operation on the channel after the current block transfer is completed. Disabling a channel in the middle of a packet transfer may result in underflow conditions in the attached application block and data loss. When a channel is disabled, the implementation may choose to reset all state for the channel. The pause bit should be asserted instead of clearing enable directly if the intent is to temporarily pause the channel. This field is encoded as follows: 0 = channel is disabled 1 = channel is enabled This field will be cleared by HW after a teardown is requested to indicate that the channel teardown is complete. Reset Source: rst_mod_g_rst_n |
| 30 | TX_TEARDOWN | R/W | 0h | Channel teardown: Setting this bit will request the channel to be torn down. This field will remain set after a channel teardown is complete. Reset Source: rst_mod_g_rst_n |
| 29 | TX_PAUSE | R/W | 0h | Channel pause: Setting this bit will cause the channel to pause processing immediately. Reset Source: rst_mod_g_rst_n |
| 28 | TX_FORCED_TEARDOWN | R/W | 0h | Channel forced teardown: Setting this bit will cause the channel to stop waiting on trigger events. When this bit is set, the implementation may choose to bypass data transfers and event generation. This bit is a modifier to the normal tx_teardown and is intended to flush the channel to recover any descriptor or TR references which are currently being held by the BCDMA even if the trigger source is no longer functioning. Use og this bit is considered a 'catastrophic' condition and it is assumed that SW will need to perform some re-initialization in the system to re-align events, data buffers, etc. This bit should be set in addition to the tx_teardown bit in order to cause a forced teardown. This field will remain set after a channel teardown is complete. Reset Source: rst_mod_g_rst_n |
| 27:1 | RESERVED | NONE | 0h | Reserved |
| 0 | TX_ERROR | R | 0h | Channel error: This bit will be set anytime an error has occurred on the channel. This bit is cleared by writing back a 0. Reset Source: rst_mod_g_rst_n |