SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Status Register provides a read only view of channel status bits.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_BCDMA_0 | 4A84 0044h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RX_REQS | RESERVED | FIFO_PEND | FIFO_BUSY | ||||
| R | NONE | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHANNEL_OK | CHANNEL_BUSY | RESERVED | IN_PACKET_ARRAY | RESERVED | |||
| R | R | NONE | R | NONE | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RX_REQS | R | 0h | The channel is sending a schedule request Reset Source: rst_mod_g_rst_n |
| 30:26 | RESERVED | NONE | 0h | Reserved |
| 25 | FIFO_PEND | R | 0h | The FIFO has enough data for a burst Reset Source: rst_mod_g_rst_n |
| 24 | FIFO_BUSY | R | 0h | The fifo has data Reset Source: rst_mod_g_rst_n |
| 23:8 | RESERVED | NONE | 0h | Reserved |
| 7 | CHANNEL_OK | R | 0h | Channel is trying to send data Reset Source: rst_mod_g_rst_n |
| 6 | CHANNEL_BUSY | R | 0h | Channel has active transactions Reset Source: rst_mod_g_rst_n |
| 5:4 | RESERVED | NONE | 0h | Reserved |
| 3 | IN_PACKET_ARRAY | R | 0h | The channel is in a packet Reset Source: rst_mod_g_rst_n |
| 2:0 | RESERVED | NONE | 0h | Reserved |